Multiprocessor computer systems can be generally divided into two categories: systems containing multiple processors having a shared common memory or having unshared distributed memories. Systems organized so that all processors have equal access to peripheral devices and shared memory are known as symmetric multiprocessing (SMP) systems. The processors within an SMP system may be connected to peripherals, shared memory and each other through a common bus, a bus hierarchy, a crossbar switch or a multistage network. In addition, the shared system memory may consist of multiple memory elements residing at different locations within the system or network.
In many of the SMP systems referred to above, the interconnection path between the various processors and memory elements may vary, resulting in different memory access times, or memory latencies, for each processor-memory combination. Access to "close" memory (for example, memory packaged on the same board as the processor) is much faster than "distant" memory (memory packaged on another processor board). In classic SMP designs employing uniform memory access (UMA), access to memory is uniformly governed by the speed of distant accesses. Memory access times are established to provide each processor with equal access time to system memory.
In a non-uniform memory access (NUMA) computer architecture, memory access latencies are allowed to differ depending on processor and memory locations. All processors in a NUMA system continue to share system memory, but the time required to access memory varies, i.e., is non-uniform, based on the processor and memory location. The main advantage of NUMA SMP designs over other alternatives to UMA SMA architectures is that, to an application or programmer, the NUMA memory model still appears as traditional SMP shared memory. As a result, NUMA systems can run existing SMP applications without modifications.
In a system wherein processors and system memory are organized into two or more nodes, such as the system illustrated in FIG. 1, discussed below, performance of a particular processor is always best if it accesses memory from its own local node rather than from a more remote node. A determination of memory access patterns of all nodes in a multi-node computer system facilitates a remapping of memory pages and processes to processors in order to optimize system performance. A determination of memory activity by cycle type, such as coherency cycles, reads, writes, copyback cache cycles, etc., provides for further refinements and improvements in the mapping of memory pages and processes to processors within a NUMA computer system.